A RISC-based ATM network interface: processing, architecture, scalability and performance
LE3 .A278 2000
Master of Science
The question of whether to design the processing core of a network interface (NI) using a custom made hardware or an embedded processor for ATM Segmentation and Reassembly function is certainly an important one that has been addressed by many NI researches. The embedded processor core can be very useful in providing the following important features to network interfaces: simplicity, shorter developing cycle time, low cost, and flexibility to support protocol changes and perhaps new protocols. However, it is not clear what the scalability of NIs would be if their designs were based on embedded RISC core to support different high-speed transmission lines. This work investigates the use of the Embedded RISC core in the ATM NI design. A cycle accurate VHDL-based simulator has been developed to measure the amount of processing required for ATM network interface design that support different transmission line speeds. The results have shown that a simple and cost effective embedded RISC core running under 85MHz can be used as a processing element in a high-speed ATM network interface. This core can support a wide range of transmission line speeds, up to 1.2Gb/s and 2.4Gb/s, for Reassembly and Segmentation functions respectively. We believe that this research can also be used as a guidance work for the ATM NI design.
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